Microwave frequency synthesizers are well known in the prior art and where they use a voltage controlled oscillator (VCO) in a single phase-locked-loop, they utilize a technique known as "fractional-N" or "digiphase" control. The basic technique is to generate small channel spacings by switching between two values of N in the feedback path of the loop where N=a frequency divider value determined by a programmable divider in the loop and connected to receive the output of the VCO. The value of N is altered at the end of every division such that over a long period of time, the average value of N is a fractional value and synthesizer output frequencies, or channels, can be created that are spaced closer together than the reference frequency would otherwise permit.
However, the smallest channel spacings depend upon the smallest change in N that can be permitted. The smallest frequency or channel spacing is limited to a value equal to the reference frequency. Generated channels spaced smaller than the reference frequency required synthesizers that used direct synthesis, multiple-phase-locked loops or a single phase-lock-loop combined with another synthesizer. All of these techniques require more than a single phase-locked-loop combined with another synthesizer.
There are several disadvantages with the prior art microwave frequency synthesizer. The fractional-N synthesizer generates significant noise and incidental frequency modulation (IFM). This noise is usually compensated with correction voltages fed into the phase detector and by narrow phase-locked-loop bandwidths. Since fast settling and narrow loop bandwidths are incompatible, the only method of getting a fractional-N synthesizer to settle quickly and to have minimal IFM is by precisely compensating the error voltage. Limits exist on how precisely this compensation can be done, which, in turns, limits the IFM suppression.
Before the existence of fractional-N synthesizers, the dual requirement of fast settling and small channel spacings could not be performed by a single phase-locked-loop.
The present invention overcomes the disadvantages of the prior art by providing a synthesizer design which permits the generation of small channel spacings without requiring a low reference frequency or a "fractional-N" implementation. This permits the synthesizer to settle quickly without generating excess IFM (from "fractional-N" division) in a single phase-locked-loop.
The wide frequency coverage is achieved by using a voltage controlled oscillator (VCO) and a parametric divider with wide band frequency coverage in a phase-locked-loop. The fast hopping capability or fast settling time, is primarily derived from the wide loop bandwidth which, in turn, is permitted by using a high reference frequency. The small channel spacings are created by using a 90.degree. phase shifter installed in the feedback path of the phase-locked-loop. The 90.degree. phase shifter permits channel spacings as small as 1/4 the reference frequency value. One primary advantage of the 90.degree. phase shifter is that the use of fixed prescaling in the phase-locked-loop does not result in the loss of channels as occurs in the prior art.
The present invention uses a voltage controlled oscillator having wide frequency coverage. Its output is coupled to a 90.degree. phase shifter which assists in enabling small channel spacings to exist. The output of the phase shifter is coupled to a fixed parametric divider which enables prescaling to exist in the phase-locked-loop. The output of the fixed divider is coupled to a programmable divider which divides the frequency according to a predetermined schedule or number. The fixed and programmable dividers, in conjunction with the voltage controlled oscillator, enable wide frequency coverage to exist in the feedback loop. The output of the programmable divider is coupled to a phase detector where it is compared with a reference frequency. The reference frequency is relatively high and, in conjunction with the wide loop bandwidth, enables a fast hopping capability or a fast settling time to exist within the single phase-locked-loop. The output of the phase detector is coupled through a loop filter back to the voltage controlled oscillator to form the feedback loop. The output frequency, f.sub.out, of the VCO is dependent upon the reference frequency, f.sub.ref, the divider value, N, of the fixed and programmable divider and the number, R, of 90.degree. phase shifts occurring in one period of the reference frequency. Thus, the phase shifter is controlled from a command center such as a memory array having a stored program or a computer which predetermines the values of R and N to enable the synthesizer to operate at a preset or predetermined frequency.